Introduction and The Well

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Book referred  == "CMOS Circuit Design, Layout and Simulation" 

                                                                         written by Jacob Baker.

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Basic components of CMOS process: 

About Silicon and Doping :   

• Number of intrinsic carriers in a pure silicon = ni = 14.5 x 10^9 carriers/cm3, therefore
  number of holes (p) in VB = number of electrons (n) in CB = intrinsic carriers (ni)
• Number of Silicon atoms = Nsi = 50 x 10^21 atoms/cm3
• If donor atoms are added to Si:
  electrons carriers (n) =(appx) Nd Number of Donor atoms, provided Nsi >> Nd >> ni
• If Acceptor atoms are added to Si:
  hole carriers (p) =(appx) Na Number of acceptor atoms, provided Nsi >> Na >> ni
• Mass-Law equation
              pn = ni^2
• Fermi- Energy Level: Indicates probability of occupation of electrons is half.
  For p-type semiconductor : Ei - Efp = kT. ln(Na/ni) Joules
  For n-type semiconductor : Efn - Ei = kT. ln(Nd/ni) Joules 
  Hence Built-In potential/ Barrier potential:
                          Vbi = (Efn - Efp) / q = (kT/q) x ln(NaNd/ni^2)
  Where :
                Ei = Fermi energy of intrinsic silicon
                Efp = Fermi energy of p-type silicon
                Efn = Fermi energy of n-type silicon

The Well :  

• An example of a well (Let us consider n-well and p-substrate in all our discussions). 
  
  
  
  
• In Oxide formation (SiO2),
  thickness of oxide = 2.2222...x thickness of silicon being used for this purpose.
  
• Depth(t) is always fixed in fabrication process, so its important to know that only things we
  worry about is L (length) and W (width).
  
  
• Parasitic Associated with n-well:  

1. Parasitic diode exists between n-well and p-substrate as shown in fig above.
   DC characteristics of the diode are given by "shockley's diode equation"
                            Id = Is (e^(Vd/nVt) - 1) Amps
                 where,
                       Id = Diode Current
                       Is = Saturation Current
                       Vd = Diode Voltage
                       Vt  = Thermal Voltage (kT/q), k = Boltzman constant
                       n(eta) = emission co-efficient                               
2. Parasitic npn/pnp bipolar transistor can exists between two n-well placed consecutively.                                  
3. Depletion layer Capacitance:
               Depletion Capacitance Cj = Cj0 / (1 - Vd/Vbi)^m
               Where :
                            Cj0 = Zero bias capacitance
                            m = grading co-efficient(showing how silicon changes from n to p-type).
4. Storage/Diffusion Capacitance:
               Storage Capacitance Cs = (Id/nVt) x Tt
               where :
                            n(eta) = emission co-efficient
                            Tt(tuo - t) = Minority Carrier Lifetime.
                            Minority Carrier Lifetime is "the time it takes an electron to diffuse
                            through junction and recombines"                    
5. Reverse recovery time associated with a Diode:
   From the fig below, 

                     Reverse Recovery time trr = t3(10% of iR) - t1
                     Storage Time (The time it takes to remove the stored charge) : 

                                     ts  = t2 - t1   or   ts = Tt x ln((iF - iR)/-iR)
                     where :
                                      iF = (Vf - 0.7) / R
                                      iR = (Vr - 0.7) / R   

• RC Delay through n-well:

• Resistance of a rectangular slab is given by,
      R = Rsquare (L/W) ohms
      where,
             Rsquare = resistivity(rho)/thickness(t) ohms
• RC circuit understanding:
      Output voltage Vout = Vpulse (1 - e^(-t/RC)) Volts
      Delay time (Vout = 50% of Vpulse) td = 0.7RC
      Rise Time tr = t90% - t10% = 2.2RC
  
        

• Distributed RC/ n-well RC circuitry:
      Delay Time td = 0.35 . Rsquare . Csquare . l^2
      Rise Time tr = 1.1 . Rsquare . Csquare . l^2